1. Field of Invention
The present invention generally relates to a level shift circuit and method thereof, and more particularly to a level shift circuit and method thereof in the LCD display apparatus.
2. Description of Prior Art
The source driver of the display has plural channels for driving data lines of the display. Each channel has level shift circuits for converting a low-voltage signal into a high-voltage signal. FIG. 1 is a schematic diagram showing a conventional level shift circuit 10. The level shift circuit 10 comprises P-MOS transistors MP1˜MP3 and N-MOS transistors MN1 and MN2. The level shift circuit 10 converts the low-voltage input signals input_sig and /input_sig into the high-voltage output signals OUT and /OUT.
The P-MOS transistors MP1 and MP2 receives the supply voltage VDDA via the P-MOS transistor MP3 which is controlled by the enable signal ENLS. The gate of the P-MOS transistor MP1 is coupled to the output terminal B, and the gate of the P-MOS transistor MP2 is coupled to output terminal A.
The N-MOS transistor MN1 is connected between the output terminal A and the ground terminal GND and controlled by the input signal /input_sig, generated by the inverter 101. The N-MOS transistor MN2 is connected between the output terminal B and controlled by the input signal input_sig. The resistor GND_LOAD is a parasitic resistor of conduction lines to emulate ground loading.
When the enable signal ENLS enable the level shift circuit 10 (i.e. ENLS=LOW) and the input signal input_sig is high, the transistors MN2 and MP1 are turned on, and the transistors MN1 and MP2 are turned off. Thus the output terminal A is pulled high, and the output terminal B is pulled low. In another state when the enable signal ENLS enable the level shift circuit 10 (i.e. ENLS=LOW) and the input signal input_sig is low, the transistors MN2 and MP1 are turned off, and the transistors MN1 and MP2 are turned on. Thus the output terminal A is pulled low, and the output terminal B is pulled high.
With the increasing size of the LCD display apparatus, the channel number of the source driver in the LCD apparatus also increases. The plural level shift circuits 10 change states simultaneously, and thus the total current flowing to the ground GND is large. Since there exists the parasitic resistor GND_LOAD, the voltage at node G′ is higher than the ground voltage and thus the voltage Vgs between gate and source of the N-MOS transistor MN1 or MN2 is smaller, which may cause the N-MOS transistor MN1 or MN2 fail to turn on.
FIG. 2 is a plot diagram showing the waveforms of the first and second output signals OUT and /OUT when the level shift circuit 10 fails. The curve 20 represents the voltage amplitude of the enable signal ENLS. The curve 21 represents the voltage amplitude of the output signal OUT at the output terminal A, and the curve 22 represents the voltage amplitude of the second output signal /OUT at the output terminal B.
Suppose that the input signal input_sig is logic high. During the transient state of the level shift circuit 10, the enable signal ENLS is first at a high level and then is asserted to a low level to enable the level shift circuit 10. When level shift circuit 10 is not enabled (the enable signal ENLS is high), the input signals input_sig and /input_sig is inputted and the output signal OUT goes from high to low (see the curves 20 and 21) because the transistor MN1 is turned on by the input signal /input_sig. The output signal /OUT is pulled to a level lower than ground since it is coupled to a low voltage by the output signal OUT through MP2 (see the circle mark 23, and the curve 22). Therefore at the next step when the level shift circuit 10 is enabled (the enable signal ENLS is at the low level), the transistor MP1 has a stronger driving than the transistor MP2, which makes the first output signal OUT be erroneously pulled high while it should be pulled low, such that the level shift circuit 10 fails.